vectorization - How to vectorize/group together many signals generated from Qsys to Altera Quartus -

in altera qsys, using ten input parallel ports (lets name them pio1 pio10), each port 12 bits. these parallel ports obtain values vhdl block in quartus schematic. in schematic bdf, can see pio1 pio10 nios ii system symbol can connect these pios other blocks in bdf.

my question is, how vectorize these pio1 pio10? instead of seeing ten pios 1 line 1 line coming out nios system symbol, should in order group these ten pios see 1 instead of ten? 1 pio see, can name pio[1..10][1..12], first bracket means pio1 pio10, second bracket means bit1 bit 12 because each parallel port has 12 bits.

could please let me know how that?