arm64 - ARMv8 exception vector significance of EL0_SP -

i new armv8 architecture , while reading v8 exception vectors not able understand significance of adding sp_el0 level vectors while sp_elx vector set exists. trying find use case useful. understand when exception taken @ same level default stack of same exception level used example if el2 (hyp) mode defined if exception occurs while being @ el2 level stack defined @ el2 used not sure if configure use el0 level stack under use cases useful ? can 1 give use case , explain ?

also while going through spec seems these 2 different stack usage idea taken cortex-m architecture not clear thread , handler modes well. can 1 explain ?

just wanted add here armv7 doesn't have thread , handler concept not clear requirement in armv8.

thanks

sp_el0 "normal" stack pointer. code runs in el should running on sp_el0 whenever can. sp_el1/2/3 "exception" stack pointer mode. when exception, fault, or interrupt happens, processor switches stack (and possibly switches el). exception handler code should needs save exception state , onto sp_el0 complete handling exception.

that is, el0 user code, el1 kernel code, el2 hypervisor, , el3 monitor should using sp_el0 except in stages of exception handlers. if take nested exception while on sp_elx (non-zero), blow on stack, elr, far, etc. why want save these , sp_el0 can.