verilog - Xilinx: Common synthesis Warnings - 


module instructionregister(ir_in,ir_out,ir_r_enable,ir_w_enable,clock);     input clock;     input [7:0] ir_in;     output reg [7:0] ir_out;     input ir_w_enable;     input ir_r_enable;     reg [7:0] insreg;     initial     begin         ir_out=8'b0;     end     @(posedge clock)         begin             if(ir_w_enable)                 insreg <= ir_in;             else if(ir_r_enable)                 ir_out <= insreg;         end endmodule

warning:due constant pushing, ff/latch unconnected in block (for 8 bits)

now, searched warning , common explanation value of register not changing here value depends on input may vary...so why warning?

your module defintely not cause of warning. it's 1 (or more) of signals go module module instantiates it.

"constant pushing" means ir_in bus connected constant value, register store same value, hence synthesizer optimizes module throwing away register.

this happens when module being tested and, commodity reasons, connect inputs constant value.


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