Testbench of floating point adder in verilog -

i want write floating point double precision adder. in test-bench of that, have problems.

*adder module gets 2 64bits number , give sum of them.

this test bench:

module testadder;   reg [63:0]           a;   reg [63:0]           b;   wire [63:0]          sum;    reg[10:0] expa,expb,expsum;   reg signa,signb,signsum,one;   reg[51:0] fa,fb,fsum;   real ta,tb,fa2,fb2,sumcheck,fsum2,resultmodulesum;   integer i;     reg [10:0]h23;  adder nameofinstance(sum,a,b); initial begin      for(i=0;i<1000;i=i+1)    begin      h23=1023;      one=1'b1;    = {$random(),$random()};    b = {$random(),$random()};    #10;     expa=a[62:52]-h23;     expb=b[62:52]-h23;     fa=a[51:0];     fb=b[51:0];     signa=a[63];     signb=b[63];     fa2 = ( $bitstoreal(fa)/(2**52) )+ 1 ;     ta=(-1)**(signa)*fa2*(2**expa);     fb2 = ( $bitstoreal(fb)/(2**52) ) + one;     tb=(-1)**(signb)*fb2*(2**expb);     sumcheck=ta+tb;     fsum=sum[51:0];     signsum=sum[63];     fsum2 = ( $bitstoreal(fsum)/(2**52) ) +one;     expsum=$bitstoreal(sum[62:52])-1023;     resultmodulesum=(-1)**(signsum)*fsum2*(2**expsum);     if(sumcheck!=resultmodulesum)       $display("wrong");    end end endmodule      module adder(sum,a, b);     input [63:0]   a;     input [63:0] b;     reg [63:0] fa,fb;     @(a or b) begin     fa={1'b1,a[51:0],12'b0};     fb={1'b1,b[51:0],12'b0};     end     endmodule 

1. when add ( $bitstoreal(fa)/(2**52) ) 1 , fa2 1 ! when don't add , fa2 real value of (fa/2^52). change code avoid adding one, problem appears!

my change making ta,tb , resultmodulesum: (example fa)

 fa2 = ( $bitstoreal(fa)/(2**52) ) ;  ta=(-1)**(signa)*(fa2*(2**expa)+(2**expa)); 

2.then understand ta (-1)**(signa)*(2**expa); means fa2*(2**expa) 0 ! don't know why , can make correct. think if didn't change fa2 , fa2 (with 1 added in it) give correct output, ta might has problem.

3.i have problem in module strange! little part of adder code module comes after test-bench code. when debug code, 63th bit of fb 0! idea?

this not full answer more can expressed in comments.

for model of floating point double have expected see along lines of:

reg [63:0] a; reg [63:0] b;  //built in real verification of code real result; real a_real; real b_real;  initial begin   = {$random(),$random()};   b = {$random(),$random()};    #1ps;   a_real = $bitstoreal(a);   b_real = $bitstoreal(b);   result = a_real + b_real;    $display("a      %64b", a);   $display("b      %64b", b);   $display("a_real %f", a_real);   $display("b_real %g", b_real);   $display("result %f",  result);    #1ps;   $finish; end 

for splitting randomised doubles in parts have expected see thing like:

wire a_sign;           // 1 bit wire [10:0] a_exponent;//11 bit wire [51:0] a_fraction;//52 bit  assign a_sign     = a[63]   ; assign a_exponent = a[62:52]; assign a_fraction = a[51:0] ;  wire b_sign;           // 1 bit wire [10:0] b_exponent;//11 bit wire [51:0] b_fraction;//52 bit  assign b_sign     = b[63]   ; assign b_exponent = b[62:52]; assign b_fraction = b[51:0] ;